WiFi MAC Design Lead Job at InnoPhase IoT, California, MO

  • InnoPhase IoT
  • California, MO

Job Description

Job Description:

Join Innophase IoT as a WiFI MAC Design Engineer/Lead and be responsible for Low-powerWiFi, BT/BLE micro-architecture and design. You will be involved in the design developmentcycle, which includes participating in high-level product specifications, RTL development,working closely with Algorithm and verification engineers.

Your specific responsibilities may include but are not limited to the following:

  • Help define and refine the WiFi LMAC micro-architecture, partition, accelerators.
  • Develop micro-architecture, and SystemVerilog RTL to meet size, timing, and power target.
  • Analyze, and identify bottlenecks in design and provide feedback on micro-architecture, andoptimizations.
  • Develop, and refine design, verification and analysis tools and flows, as needed.
  • Work closely with Verification, and Validation teams on test-plans, coverage-analysis
  • Work closely with Design teams to provide guidance on Floor planning, specification of
    constraints, and timing closure.

Required Qualifications:

  • Solid understanding of wireless standards, such as IEEE 802.11, 802.15, Bluetooth is a plus
  • Understanding of WiFi MAC HW requirements and prior hands-on experience design
  • Expertise in working w/ APB/AHB/AXI bus protocols.
  • 7+ years of experience in RTL design using Verilog, SystemVerilog
  • BSEE or MSEE, with experience in ASIC development and/or FPGA prototyping
  • Ability to work independently, and proactively identify and resolve issues.
  • Experience with Incisive/Excellium/VCS, Verdi, Jasper/Spyglass or equivalent tools
  • Experience in partitioning, synthesis, placement, timing closure for FPGA and/or ASICs
  • Experience with front-end design and integration tasks including lint, CDC, synthesis, and developing timing ECOs.
  • Enjoy debugging, and problem solving in a team environment.

Preferred Qualifications:

  • Experience in Low Power design development, involving multiple power, and voltage domains.
  • Familiar with DFT insertion, and multi-mode timing constraints is a strong plus.
  • Experience with Python, Perl, Tcl, C/C++ and shell scripts.
  • Experience with lab debug, multi-team, multi-site working environment is a strong plus.
  • Experience with ASIC and FPGA synthesis flows utilizing industry leading flows.
  • Experience using PowerArtist/Joules and providing actionable feedback into design.

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